The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs.
Another aspect of the IC evolution involves increased IC design complexity and shortened time-to-market. Designers generally face a demanding project schedule from IC conception to IC production. To meet these challenges, designers generally use modular design and hierarchical design approaches, aided by design automation tools, such as Computer Aided Design (CAD) tools. For example, a cell is designed to include multiple components, such as resistors, capacitors, and transistors, interconnected to achieve certain functionality. Then, the cell, as a unit, is replicated and placed in different parts of a design where the same functionality is needed.
In some IC designs, matching of certain characteristics of two cells is critical for the circuit performance and an offset between them may present issues. The offset between the two cells may be directed to a relative difference between two cells. Alternatively, the offset may be directed to an absolute difference between the cells. Moreover, characteristics of a semiconductor component are generally affected by its surrounding components in a design layout, such as pattern density uniformity, as well as manufacturing processes, such as thermal related process, substrate uniformity, etc. Simply placing two replications of a cell into a design layout may not achieve a desirable matching effect.
Accordingly, what is needed is improvement in this area.